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Design and Simulation of Communication Code Waveform Based on VHDL
Introduction Signal transmission can generally be divided into two major parts: encoding and decoding. The coding requirement selects an appropriate coding mode according to the characteristics of the transmitted signal. Since different signals are transmitted in different environments, the interference is different, and choosing the appropriate coding method can avoid interference to the utmost, and make the communication smoother and more accurate. The key to achieving different coding methods is to find the right algorithm and the algorithm must be simple and compatible. Here I mainly use the contrast, joint and modular design methods to make each code a separate module, but share the same clock or multiple clocks. Thereby, the storage space of the program is greatly saved, and the debugging time of the program is reduced. The article will use VHDL to design eight common coding methods, and use ALTERA's QUARTUSII design software for simulation debugging. QUARTUSII design software is an open, architecture-independent, multi-platform, fully integrated, rich design library, modular tools, support for a variety of HDL, and a variety of advanced programming language interfaces with very advanced EDA tools. In addition, the ultra-high-speed hardware description language VHDL has a powerful language structure, multi-level description function, good portability and fast ASIC conversion capability, supporting hardware design, synthesis, verification and testing. Therefore, the application of VHDL to design communication coded waveforms is of great significance. The overall design of the overall plan design is shown in Figure 1. First of all, when writing programs in VHDL, you must follow the system rules and call them according to the system library functions. Otherwise, the compilation will cause problems. Secondly, considering the sub-module programming, each encoding method will use different frequency clocks. Therefore, the system clock should be divided by two, four and eight. Then we have to design a selection module to facilitate the free choice of eight encodings. Then, the VHDL coding of each coding module is performed, and then the simulation can be compiled one by one. Finally, when each module is compiled and simulated, it is necessary to integrate each individual module program to form a total encoding program and debug the general program. Figure 1 Overall design flow chart unit module design and debugging frequency division module working principle The so-called frequency division is to generate a digital output signal with a higher frequency, after appropriate processing, to produce one or several lower frequency digital output signal. The frequency division is essentially a change of the adder. The count value is determined by the frequency division constant N=fin/fout (fin is the input frequency, fout is the output frequency), and the output is not the general counter count result, but is based on the frequency division constant. The high and low levels of the output signal are controlled. Software Design The following is a crossover procedure for dividing the input clock signal by 2, 4 and 8 divide. According to the actual needs, you can also design a frequency divider with a frequency division factor of 2N. You only need to implement a modulo N counter, and then directly apply the highest bit of the modulo N counter to the output signal of the frequency divider to get the required signal. Divided signal. The even-numbered divider block diagram with a division factor of 2 is the same as shown in Figure 2. Figure 22, 4, and 8 divider RTL block diagram In this program, rst is active low. If the divide-by-2 circuit is implemented, the most significant bit count(0) is output, and the divide-by-4 circuit outputs the most significant bit count(1). ), and so on, the most significant bit count(2) is output by divide-by-8. The simulation waveform is compiled in the MAX-plusII environment as shown in Figure 3. Figure 32, 4, and 8 frequency division waveform selection module working principle This module is used to select the signal. When inputting multiple signals, only one of the outputs is selected. The selection is based on the signal of the address line and the address line. With N, you can make a 2N selector. Software design According to the working principle of the selection module, the selector module diagram written by VHDL is shown in Figure 4. The module diagram selector program of the Figure 4 selector compiles the simulation waveform in the QUARTUSII environment as shown in Figure 5. Figure 5 selector waveform function module NRZ-L (non-return to zero code) NRZ-L (flat) code, whether 1 or 0, the adjacent symbol level polarity does not change, that is, the clock divided by 4 in the clk The rising edge outputs a signal encoder-out as the input signal din changes. The specific VHDL module diagram is shown in Figure 6. Figure 6 NRZ-L (flat) module diagram program Compile the simulation waveform in the QUARTUSII environment as shown in Figure 7. Fig. 7 NRZ-L code waveform NRZ-M (signal difference code) NRZ-M signal differential code, when it is 1, the adjacent symbol level polarity changes, and when 0, the adjacent symbol electrode polarity does not change, that is, at the clock clk The rising edge of divide by 4 is hopped by the input signal datain1, and 0 is the output signal encoder-out. The specific VHDL module diagram is shown in Figure 8. Figure 8 NRZ-M (Signal Differential Code) module diagram program Compile the simulation waveform in the QUARTUSII environment as shown in Figure 9. Figure 9 NRZ-M code waveform NRZ-S (space differential code) NRZ-S (space differential code), when 0, the polarity of the adjacent symbol level changes, and the polarity of the adjacent symbol does not change when 1 is NRZ-M (signal differential code) is just the opposite, clk is divided by 4. The specific VHDL module diagram is shown in Figure 10. Figure 10 NRZ-S (space differential code) module diagram program Compile the simulation waveform in the QUARTUSII environment as shown in Figure 11. Figure 11 NRZ-S code waveform RZ (unipolar return-to-zero code) In the return-to-zero code RZ, the signal in the middle of the symbol returns to the 0 level, so any two symbols are separated by a 0 level. When it is 1, it is 0. When it is 0, it is 0. That is, the input datain signal is separated by the middle, the clock clk is divided by 2, the rising edge encounters 1 transition, the other is 0, and the output signal encoder-out. The specific VHDL module diagram is shown in Figure 12. Figure 12 RZ (unipolar return to zero code) module diagram program Compile the simulation waveform in the QUARTUSII environment as shown in Figure 13. Figure 13 RZ Code Waveform Integral Manchester Code Manchester code is a two-phase code. In addition to the intermediate occurrence of the transition, when it is 0, the polarity of the adjacent symbol level changes, and the polarity of the adjacent symbol does not change at 1 time. Since the input datain signal is to be hopped in the middle, two clocks clk1 and clk2 are required. , and clk1 is divided by 4, clk2 is divided by 2, all of them jump at 0 on the rising edge of two clocks, and when they are held, the output signal encoder-out. Its specific VHDL module diagram is shown in Figure 14. Figure 14 is a block diagram of the Manchester code. The simulation waveform is compiled in the QUARTUSII environment as shown in Figure 15. Figure 15 Integral Manchester code waveform two-phase-M code two-phase-M code: In addition to the jump of the polarity of the adjacent symbol level, when it is 1, the middle jump occurs, when it is 0, there is no jump in the middle. That is, the clock clk1 is divided by 4, and the polarity of the adjacent signal of the input signal datain jumps. When it encounters 1, it jumps on the rising and falling edges of the clock clk1, and outputs the signal encoder-out. The specific VHDL module diagram is shown in Figure 16. Figure 16: Dual-phase-M code block diagram program Compile the simulation waveform in the QUARTUSII environment as shown in Figure 17. Fig. 17 Biphase-M code waveform biphase-L code biphasic-L code, except for the occurrence of a transition in the middle, when 1 is the polarity of the adjacent symbol level changes, and when 0, the polarity of the adjacent symbol does not change. That is, the clock divided by clk1 is required, and the datain signal jumps outside the rising edge of the clock clk1, and the polarity of one adjacent symbol changes, 0 is unchanged, and the output signal encoder-out. The specific VHDL module diagram is shown in Figure 18. Figure 18 Biphase-L program Compile the simulation waveform in the QUARTUSII environment as shown in Figure 19. Fig. 19 Biphase-L code waveform biphase-S code biphase-S code, except for the polarity of the adjacent symbol level polarity, when there is 0, the middle jump occurs, and when it is 1, the middle does not jump. Change, that is, contrary to the two-phase-L code, clk1 is divided by four. The specific VHDL module diagram is shown in Figure 20. Figure 20 Block diagram of the module code of the dual-phase-S code The simulation waveform is compiled in the QUARTUSII environment as shown in Figure 21. Figure 21 Biphase-S code waveform overall program debugging The overall simulation program in the MAX-plusII environment is shown in Figure 22. Figure 22 Summary of eight coded waveforms 1) It is feasible to write the above eight codes using VHDL. 2) After observing the simulation waveform of each module, it conforms to the characteristics of each code. 3) Through the debugging of the overall program, and the key selection of the waveform is implemented on the FPGA. (This article Source: Alibaba)